In designing an advanced digital integrated circuit (IC), designers typically rely upon electronic design automation (EDA) software to help create a circuit schematic design consisting of millions or tens of millions of individual devices that are coupled together to perform highly complex circuit functions. Such devices include, among other things, basic logical units that perform basic logical functions. These basic logical units can be combinational cells, such as logic gates, adders and sequential cells, such as flip-flops, latches, and memories. The information of these basic logical units is typically stored in a standard cell library, which may include thousands of basic logical units usable in implementing an advanced IC design. These basic logical units are also generally referred to as design library cells.
Typical library cell information includes cell propagation delay, cell pin capacitance, cell output slew, etc. For sequential cells, such as registers and latches, library cell information also includes setup and hold time requirements. Timing information such as cell propagation delay and setup/hold time requirements are typically stored in cell timing libraries. The accuracy of the data in cell timing libraries is an important factor in determining the overall timing performance at which a particular circuit design can operate. As an example, the setup and hold time requirements of sequential cells are used to verify the timing of a synchronous circuit design. If characterization of the timing constraints is inaccurate, the results can be either highly optimistic or pessimistic. The optimistic case can cause a fabricated circuit to fail whereas the pessimistic case can unnecessarily degrade circuit performance, making it more difficult to achieve a target frequency.
FIG. 1 illustrates a simplified D flip-flop 10 for purposes of describing setup/hold time requirements and propagation delay (also sometimes referred to as cell timing arc). Simplified D flip-flop 10 comprises a data input terminal D, a clock input terminal CK, and an output terminal Q. The setup time requirement (Ts) is the minimum time period required for data to be valid (i.e., stable) on a data input pin D before a clock sampling edge of the clock signal CK arrives. The reason for this requirement is that a signal has a propagation speed that is dependent on the medium in which it travels. Specifically for a D flip-flop, the requirement is needed due to the time necessary to charge stray capacitance at the input pin of a D flip-flop, hence requiring the data bit to be at the data input pin D before the clock edge arrives.
Hold time (Th) can be thought of as the inverse of the setup time with respect to the reference clock edge. The hold time requirement is the minimum time period required for the data to be valid (i.e., stable) on a data input pin D before a reference clock edge in order to ensure that the input data captured on the reference edge does not change. The requirement is necessary to ensure that the data bit D is held constant long enough for the internal transistors for active devices to switch states.
Propagation delay (Tpd) occurs as a combination of active devices that can not switch states immediately and the delay in time of an input signal through its input path to its output path. Switching time is the typical cause of propagation delay. Propagation delay is generally represented by the amount of time it takes for the output of a logical cell (combinational or sequential) to change state after the input changes.
A common approach to characterizing setup/hold time for a sequence cell is typically performed on a plurality of sequence cells because the setup/hold time on a single sequence cell is typically very small and setup/hold time characterization precision on a single sequence cell is limited by the measurement error of an existing characterization setup. In order to detect the signal edges and check the delayed signal edge alignment, complex analog characterization circuit is typically employed, which requires increased IC substrate areas. As another problem of an existing characterization setup, the characterization precision is limited by the variation between the process, operating voltage and operating temperature on the plurality of sequence cells under characterization. These and other problems in an existing characterization setup limit the characterization precision above the tens of picoseconds range.